The Digital Up Conversion consists of an interpolating filter chain, a numerically controlled oscillator (NCO), and a mixer (DUC). The filter chain consists of a lowpass interpolator, halfband interpolator, CIC compensation interpolator (FIR), CIC interpolator, and CIC gain correction.
The DUC's exact Fpass and Fstop characteristics are achieved via the first lowpass interpolator. A halfband filter is a type of interpolator that lies in the center of the road. Because sample rates are lower at the start of the chain, the earlier filters might share multipliers to maximize resource utilization. When interpolating by two, the CIC compensation interpolator enhances the spectral response by accounting for later CIC droop. The interpolation factor of the CIC interpolator is high enough for filter chain upsampling.
To obtain an output sample rate of 270.83 kHz, the DUC uses an input Interpolation Factor of 2 and a decimation factor of 256. LTE receivers commonly use a sample rate of 1.92 Msps for cell search and master information block (MIB) recovery. The Digital Upconverter filters are designed particularly for this use. The DUC was created with a clock rate of 122.88 MHz in mind.
Conversion Features and Process:
- 70 MHz IF, 2.5.8, & 22MHz BWs (3dB)
- 204.8 MHz DAC Sample Rate
- The modem provides a 25 kHz fine-tune step
- Receiver / Exciter minimum freq step = 0.5 MHz, settling time < 100 us to 100Hz
- Basebang samples are converted to 70 MHz “digital IF”.
- Polyphase filter approach reduces the required 204.8 Msps processing to the simple data transfer.
- 208.8 Msps DAC sample rate required to reduce DAC sinx/x roll-off.
- The final 2x interpolation process employs parallel FIR filters that process at a 1x rate.
- As a result of the quarter-wave frequency shift, the number of filter taps is reduced by a factor of two.
- Maintain 16 bits in/out of DDC.
- Complex mixer functions should keep 18 bits at the input and truncate to 16 bits at the output.
- Digital Upconverter shares a single DDS FPGA instantiation.
- DUC shares the same FPGA filter structures.
To know more about Digital Up-Conversion.
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